Learning verilog….

So it’s not as bad as you first might think. It turns out that real time logic isn’t much different from process logic. Tho I did fall at the first hurdle:

So apparently the file name has to be the same as the entity name and that needs to be the top level entity. Furthermore the module inside it needs to have the same name also.

oh, and ‘end module’ is actually ‘endmodule’, or it will fail to compile!

(This is in QuartusII FYI.)

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